A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC

Kenichi Ohhata; Daiki Hayakawa; Kenji Sewaki; Kento Imayanagida; Kouki Ueno; Yuuki Sonoda; Kenichiro Muroya

doi:10.1109/TVLSI.2018.2827943

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC

Sept. 2018, pp. 1777-1787, vol. 26

DOI Bookmark: 10.1109/TVLSI.2018.2827943

Authors

Kenichi Ohhata, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Daiki Hayakawa, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Kenji Sewaki, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Kento Imayanagida, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Kouki Ueno, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Yuuki Sonoda, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Kenichiro Muroya, Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan

Keywords

Logic Gates, Time Domain Analysis, Signal Processing, Calibration, CMOS Technology, Capacitors, Power Dissipation, Flash Analog To Digital Converter ADC, Pipeline, Subranging, Time Based ADC TB ADC, Vernier Time To Digital Converter TDC

Abstract

In this paper, we propose a time-based analog-to-digital converter (ADC) architecture combining a flash ADC and vernier time-to-digital converter (TDC) to achieve both high speed and high resolution. The flash ADC and vernier TDC are pipelined to increase the conversion speed. A charge-steering amplifier is used for low-power residue transfer. A common level adjuster is added to the output stage of the charge-steering amplifier to stabilize the output common level against process, voltage, and temperature variation. Moreover, the vernier TDC using a dynamic delayer enables low-power operation. An 8-bit ADC test chip fabricated with 65-nm CMOS technology had a high sampling frequency (900 MHz) and low power consumption (3.5 mW). The figure of merit was 32 fJ/conversion step.

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A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC

Authors

Keywords

Abstract

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