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Published Articles >> Table of Contents >> Abstract
21st International Conference on VLSI Design (VLSI Design 2008)
pp. 421-427
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Deepa Kannan
Aseem Gupta
Aviral Shrivastava
Nikil D. Dutt
Fadi J. Kurdahi
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.84
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| Abstract |
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Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and thread- level parallelism by issuing instructions from different threads in the same cycle. However, the issues of power and thermal man- agement hinder SMT processors fabricated in nano-scale tech- nologies. Power and thermal issues in SMT processors not only limit the achievable performance, but also have a direct impact on the cost and viability of these processors. While several per- formance simulation tools to explore the performance aspect of SMT processors early in their design phase exist, there is a lack of early power and performance evaluation tools for SMT pro- cessors. To this end, we have developed PTSMT: a tightly cou- pled power, performance and thermal exploration tool for SMT processors. In this paper, we demonstrate that PTSMT can au- tomatically and effectively accomplish power, performance and thermal exploration of SMT processors at various levels of de- sign hierarchy, at the application level, microarchitecture level, and physical level. Our experimental results show that: at the application level, number of contexts into which an application is divided could affect performance by 2.2x, energy by 52%, and peak temperature by 35oC; and at the microarchitecture level, context swapping during run time could reduce energy by 9% and improve performance by 8%. These observations indicate the size of the design space which can be explored using PTSMT.
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Additional Information
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Citation:
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi,
"PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors,"
vlsi-design,
pp. 421-427,
21st International Conference on VLSI Design (VLSI Design 2008),
2008
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