| Abstract |
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A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speeding up the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.
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 Additional Information
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Citation:
Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs, hartanto@dtc.hp. com,
"Diagnostic Test Pattern Generation for Sequential Circuits,"
vts,
p. 196,
15th IEEE VLSI Test Symposium (VTS'97),
1997
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