2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)
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Abstract

In this paper we present ultra low voltage low power CMOS logic. The low power gate may be configured or recharged to high speed or low power compared to a complementary inverter. The low power logic presented in this paper resembles precharge CMOS logic. For a low supply voltage a sleep mode configuration is presented which may reduce the power consumption to less than 0.5% of a complementary inverter. A sleep mode configuration of the low power logic is presented and a keeper function is added to increase the noise margin and reduce the static power consumption. Simulated data for a STM 90nm process using Spectre simulator provided by Cadence is included.
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