Abstract
In this paper we investigate the problem of multiple multiplexing DA and AD converters in respect to the sample synchronicity. Different proposals for solution are presented. We show a method to synchronize multiple multiplexed high speed DA and AD converters in FPGAs. The method determines the phase difference between the data clocks of two DA/AD converters, but avoids shifting the input/output data and dealing with multiple clock domains. Specific hardware setup and FPGA implementation details are analyzed and taken into account as well.