2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Download PDF

Abstract

This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory, from Boolean equation to hybrid MOS/RS-NVM tree, is deeply detailed. Read and write design guideline, regarding RS-NVM and MOS resistance balance are investigated. Practical implementation is given through transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the concept by using CMOS 40 nm design kit and memory compact models.
Like what you’re reading?
Already a member?Sign In
Member Price
$11
Non-Member Price
$21
Add to CartSign In
Get this article FREE with a new membership!

Related Articles