2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
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Abstract

This paper presents the design of an SRAM cell with a robustness improvement against laser-induced fault injection. We report the fault sensitivity mapping of a first SRAM design. A careful analysis of its results combined with the use of an electrical model at transistor level of the photoelectric effect induced by a laser permit us to validate our approach. The robustness improvement is due to a specific layout which takes into account the topology of the cell and to the effect of a triple well implant on the laser sensitivity of NMOS transistors.
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