Abstract
Microarchitectures often relax order constraints to meet performance requirements. However, the design of a module handling out-of-order behaviors is error prone, since order relaxation asks for sophisticated control. Besides, its functional verification is challenging, because the module does not preserve at its output the order corresponding to its input data, violating a basic assumption of conventional scoreboards. This paper discusses the verification guarantees of three classes of dynamic checkers and experimentally compares their effectiveness and effort. Results show that a well-designed relaxed scoreboard can achieve the same effectiveness as a complete post-mortem checker with an effort similar to a conventional scoreboard's.