Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing

Abstract: We explain differences between testing delay faults in FPGAs and testing delay faults in circuits whose combinational sections can be represented as gate networks. We formulate - in a form suitable for analysis of LUT-based FPGAs - conditions that allow one to check whether or not a given input pair is a test of specific type (non-robust, robust, etc.). The presented theoretical results are shown to simplify an analysis of the various methods for enhancing the effectiveness of detection of FPGA delay faults.