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2011 IEEE/ACM International Symposium on Nanoscale Architectures

Scalability and design-space analysis of a 1T-1MTJ memory cell

Year: 2011, Pages: 32-36

Authors

Richard Dorrance, Department of Electrical Engineering, University of California, Los Angeles, USA  
Fengbo Ren, Department of Electrical Engineering, University of California, Los Angeles, USA  
Yuta Toriyama, Department of Electrical Engineering, University of California, Los Angeles, USA  
Amr Amin, Department of Electrical Engineering, University of California, Los Angeles, USA  
C.-K. Ken Yang, Department of Electrical Engineering, University of California, Los Angeles, USA  
Dejan Markovic, Department of Electrical Engineering, University of California, Los Angeles, USA
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Abstract

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.
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