A BIST Circuit for IDDQ Tests

Masaki Hashizume; Teppei Takeda; Hiroyuki Yotsuyanagi; Takeomi Tamesada; Yukiya Miura; Kozo Kinoshita

doi:10.1109/ATS.2003.1250843

2003 Test Symposium

A BIST Circuit for IDDQ Tests

Year: 2003, Pages: 390

DOI Bookmark: 10.1109/ATS.2003.1250843

Authors

Masaki Hashizume, University of Tokushima
Teppei Takeda, University of Tokushima
Hiroyuki Yotsuyanagi, University of Tokushima
Takeomi Tamesada, University of Tokushima
Yukiya Miura, Tokyo Metropolitan University
Kozo Kinoshita, Osaka Gakuin University

Abstract

An IDDQ test time reduction method is proposed which is suitable for BIST approaches in this paper. Also, a BIST circuit for IDDQ tests based on the method is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performances are evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using the test circuit.

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A BIST Circuit for IDDQ Tests

Authors

Abstract

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