Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and  Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology

Koushik K. Das; Richard B. Brown

doi:10.1109/ICVD.2003.1183152

VLSI Design, International Conference on

Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology

Year: 2003, Pages: 291

DOI Bookmark: 10.1109/ICVD.2003.1183152

Authors

Koushik K. Das, University of Michigan
Richard B. Brown, University of Michigan

Abstract

As supply voltage is scaled to below 1 V, leakage power becomes significant in CMOS ICs. This paper proposes novel circuit techniques in PD-SOI technology to reduce standby power in the sub-1 V regime by over three orders of magnitude while maintaining circuit speed and with minimal overhead. Simulation results obtained using process parameters from an IBM 0.13 m PD-SOI technology show considerable improvement over previously proposed methods as supply voltage is scaled to 0.5 V. A new design algorithm for efficient implementation of these PD-SOI standby power reduction schemes is also described.

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Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology

Authors

Abstract

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