HW/SW approaches to accelerate GRAPES in an FU array

Wei Wang; Jun Yao; Youhui Zhang; Wei Xue; Y. Nakashima; Weimin Zheng

doi:10.1109/CoolChips.2013.6547920

IEEE Symposium on Low-Power and High-Speed Chips. 2013 COOL Chips XVI

HW/SW approaches to accelerate GRAPES in an FU array

Year: 2013, Pages: 1-3

DOI Bookmark: 10.1109/CoolChips.2013.6547920

Authors

Wei Wang, Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Jun Yao, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan
Youhui Zhang, Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Wei Xue, Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Y. Nakashima, Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan
Weimin Zheng, Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China

Abstract

In this research, a high performance computing weather forecasting application GRAPES has been tuned onto a functional unit (FU) array based architecture. Software and hardware approaches are specifically employed to increase the data locality and data reuse to accelerate the stencil computation in GRAPES. The simulation results indicate that we can achieve a per-core average IPC of 12.3 within a 20-stage FU array processor, which has a 5.8x power-efficiency boost than the many-core processor (MCP) of a same process technology. This can accordingly slow down the increase of communication by one order in the cluster system, resulting in a 12x power-efficiency boost in all PEs.

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HW/SW approaches to accelerate GRAPES in an FU array

Authors

Abstract

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