Hardware efficient design of Variable Length FFT Processor

Vinay Gautam; Kailash Chandra Ray; Pauline Haddow1

doi:10.1109/DDECS.2011.5783102

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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

Hardware efficient design of Variable Length FFT Processor

Year: 2011, Pages: 309-312

DOI Bookmark: 10.1109/DDECS.2011.5783102

Authors

Vinay Gautam, Department of Computer and Information Science, NTNU, Trondheim, Norway-7491
Kailash Chandra Ray, Department of Electrical Engineering, Indian Institute of Technology, Patna, India-800013
Pauline Haddow1, Department of Computer and Information Science, NTNU, Trondheim, Norway-7491

Hardware efficient design of Variable Length FFT Processor

Authors

Abstract