Test and configuration architecture of a sub-THz CMOS detector array

Péter Földesy; Domonkos Gergelyi; Csaba Fűzy; Gergely Károlyi

doi:10.1109/DDECS.2012.6219033

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Test and configuration architecture of a sub-THz CMOS detector array

Year: 2012, Pages: 101-104

DOI Bookmark: 10.1109/DDECS.2012.6219033

Authors

Péter Földesy, The Computer and Automation Research Institute, MTA-SZTAKI, Hungarian Academy of Sciences, Budapest, Hungary
Domonkos Gergelyi, Faculty of Information Technology, Péter Pázmány Catholic University, PPKE-ITK, Budapest, Hungary
Csaba Fűzy, Department of Broadband, Infocommunicatons and Electromagnetic Theory, Budapest University of Technology and Economics, Hungary
Gergely Károlyi, Department of Broadband, Infocommunicatons and Electromagnetic Theory, Budapest University of Technology and Economics, Hungary

Abstract

This paper describes the architecture and testability issues of a 90 nm CMOS sub-THz detector array ASIC. The sub-THz detector array is an integrated system composed of silicon field effect plasma wave sensors, integrated antennas, pre-amplifiers, ADCs, and digital domain lock-in amplifier detector. The mixed-signal system is controlled and monitored by JTAG interface containing several access points and multiple power domains. The peak responsivity is found 185 kV/W@365 GHz and at the detectivity maximum the NEP ~ 20 pW/Hz-1.

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Test and configuration architecture of a sub-THz CMOS detector array

Authors

Abstract

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