Abstract
One of the common methods for system behavior verification and performance estimation is high-level modeling using SystemC. A SystemC design represents parallel components of the system and their interconnections, so it is important to ensure that the design does not have synchronization errors: deadlocks, livelocks, and data races. In this paper we propose a novel approach to data races detection in SystemC designs. Our approach is based on static analysis methods and allows to detect data race errors automatically. The approach provides sound results. It includes special approximations and heuristics for a good balance between scalability and precision.We show the efficiency of our approach by evaluating it on basis of artificial and real-world SystemC designs.