2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
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Abstract

The paper presents a testing method for cache memories of specific processor core. The proposed method uses specially designed scalable MBIST architecture to perform all desired test operations and is independent of memory cache type. The designed MBIST architecture allows performing tests even during processor's functional mode which is the main advantage over software-based solutions. Achieved results are demonstrated by test execution time.
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