2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
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Abstract

A novel resistance calculation method based on eigen calculus of the circuit's nodal admittance matrix is described and evaluated in this paper. More specifically, the calculation time efficiency of the method is examined and comparison to the traditional LU factorization based method is made. This evaluation is based on real and complex matrices that are both symmetrical and non-symmetrical as well. Circuits sizes taken into account range from 25 to 3600 nodes. The obtained results demonstrate the time efficiency of this method, especially, for non-symmetrical matrices. The proposed method could be used to speed-up the fault simulations and improve test development of analog circuits.
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