Abstract
This paper presents a case for using automatically generated transaction level models (TLMs) for high level design. The inputs to automatic TLM generation are application C tasks mapped to processing units in the platform. Based on the mapping, the basic blocks in the C tasks are analyzed and annotated with estimated delays. The delay-annotated C code is linked with a SystemC model of the platform's communication architecture to generate the TLM. The TLM is compiled and executed natively on the host machine, making it much faster than conventional cycle accurate models. TLMs for industrial scale designs such as MP3 decoder have been shown to simulate in seconds, compared to 3–4 hrs of instruction set simulation (ISS) and 15–18 hrs of RTL simulation. Timing estimation error over board simulation has been shown to be less than 15%.