2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)
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Abstract

Hardware Trojans (HTs) have been generally inserted at the lower levels of the digital system design and fabrication process, where, due to the high complexity of the hardware model, their detection is more difficult. However, RTL models are becoming more and more complex, making difficult the identification of malicious behaviours also at this level. Unfortunately, only a few verification techniques have been proposed for the identification of HTs in RTL descriptions. To fill in the gap, this paper proposes a technique that exploits graph-based features and a probabilistic neural network to identify and classify HTs at RTL. The approach identifies suspicious locations inside the RTL description according to a set of known HTs. In addition, it returns a couple of similarity indexes to measure the probability that a suspicious location actually contains a malicious behaviour.
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