Importance sampled circuit learning ensembles for robust analog IC design

This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. ISCLEs consists of: (1) a boosting algorithm developed specifically for circuit assembly; (2) an ISCLEs-specific library of possible digital-sized circuit blocks; and (3) a recently-developed multi-topology sizing technique to automatically determine each block’s topology and device sizes. ISCLEs is demonstrated on design of a sinusoidal function generator and a flash A/D converter, showing promise to robustly scale with shrinking process geometries.