Abstract
With advances in semiconductor process technology, chip power density has dramatically increased, making power grid integrity a critical concern at all stages of the design process. Given the inherent difficulty of capturing worst-case IR drops for all logic gates with dynamic vectors, a static flow is essential for verifying grid integrity on complex chip designs, especially microprocessors. A novel static transistor-level IR drop analysis flow which significantly reduces the conservatism of other static flows is presented. The key feature of this flow is a fast NAND decision diagram (NDD) algorithm, a lightweight variant of a boolean decision diagram (BDD) with the capacity to effectively process device transition exclusions in a per logical-device, context-sensitive fashion, thereby radically reducing the conservatism typical of static analysis.