FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Shahnam Mirzaei; Anup Hosangadi; Ryan Kastner

doi:10.1109/ICCD.2006.4380833

2006 24th International Conference on Computer Design

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Year: 2006

DOI Bookmark: 10.1109/ICCD.2006.4380833

Authors

Shahnam Mirzaei, University Of California, Santa Barbara, CA 93106. E-mail: shahnam@umail.ucsb.edu
Anup Hosangadi, University Of California, Santa Barbara, CA 93106. E-mail: anup@ece.ucsb.edu
Ryan Kastner, University Of California, Santa Barbara, CA 93106. E-mail: kastner@ece.ucsb.edu

Abstract

We present a method for implementing high speed finite impulse response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common subexpression elimination algorithm to reduce the number of adders. We target our optimizations to Xilinx Virtex II devices where we compare our implementations with those produced by Xilinx CoregenTM using Distributed Arithmetic. We observe up to 50% reduction in the number of slices and up to 75% reduction in the number of LUTs for fully parallel implementations. We also observed up to 50% reduction in the total dynamic power consumption of the filters. Our designs perform significantly faster than the MAC filters, which use embedded multipliers.

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FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Authors

Abstract

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