CMOS logic design with independent-gate FinFETs

Anish Muttreja; Niket Agarwal; Niraj K. Jha

doi:10.1109/ICCD.2007.4601953

25th International Conference on Computer Design, ICCD 2007

CMOS logic design with independent-gate FinFETs

Year: 2007

DOI Bookmark: 10.1109/ICCD.2007.4601953

Authors

Anish Muttreja, Dept. of Electrical Engineering, Princeton University, NJ 08544 USA
Niket Agarwal, Dept. of Electrical Engineering, Princeton University, NJ 08544 USA
Niraj K. Jha, Dept. of Electrical Engineering, Princeton University, NJ 08544 USA

Abstract

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logic style is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

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CMOS logic design with independent-gate FinFETs

Authors

Abstract

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