Abstract
Sub-wavelength lithography causes the shape of transistors to differ from idealized rectangles. Several researchers have proposed transistor simulation models to characterize the non-ideal shapes of transistors for various regions of transistor operation. It has been shown that the effective channel length of a non-rectangular gate (NRG) transistor may be different for ON and OFF currents. In this paper we present a composite post-litho non-rectangular transistor model that not only accounts for DC behavior of a transistor, but also accounts for parasitic capacitances across a range of voltages. Parameters of this model can be fitted to real silicon data. The proposed model has been validated by TCAD device simulations. Results show that a composite model that accounts for both DC currents and parasitic capacitances is no more complex than models optimized for DC currents only. Further, the proposed model integrates readily with available SPICE simulators. We have also presented cell library characterization data to illustrate the benefit of using a delay accurate transistor model.