Design and evaluation of a delay-based FPGA Physically Unclonable Function

Phillip Jones; Joseph Zambreno; Christopher Sabotta; Michael Patterson; Sudhanshu Vyas; Aaron Mills

doi:10.1109/ICCD.2012.6378632

2012 IEEE 30th International Conference on Computer Design (ICCD 2012)

Design and evaluation of a delay-based FPGA Physically Unclonable Function

Year: 2012, Pages: 143-146

DOI Bookmark: 10.1109/ICCD.2012.6378632

Authors

Phillip Jones, Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Joseph Zambreno, Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Christopher Sabotta, Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Michael Patterson, Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Sudhanshu Vyas, Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA
Aaron Mills, Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA

Abstract

A new Physically Unclonable Function (PUF) variant was developed on an FPGA, and its quality evaluated. It is conceptually similar to PUFs developed using standard SRAM cells, except it utilizes general FPGA reconfigurable fabric, which offers several advantages. Comparison between our approach and other PUF designs indicates that our design is competitive in terms of repeatability within a given instance, and uniqueness between instances. The design can also be tuned to achieve desired response characteristics which broadens the potential range of applications.

Like what you’re reading?

Already a member?

Get this article FREE with a new membership!

Model building attacks on Physically Unclonable Functions using genetic programming
2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
FPGA based trustworthy authentication technique using Physically Unclonable Functions and artificial intelligence
2012 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2012)
Design and Implementation of a Delay-Based PUF for FPGA IP Protection
2013 International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics)
Fault Tolerant Implementations of Delay-Based Physically Unclonable Functions on FPGA
2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)
Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
Laser Fault Attack on Physically Unclonable Functions
2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)
The Impact of Aging on an FPGA-Based Physical Unclonable Function
International Conference on Field Programmable Logic and Applications
Compact Implementations of FPGA-based PUFs with Enhanced Performance
2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)
Improving the Reliability of FPGA CRO PUFs
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
Area Constraint Aware Physical Unclonable Function for Intelligence Module
2018 3rd International Conference on Computational Intelligence and Applications (ICCIA)

Design and evaluation of a delay-based FPGA Physically Unclonable Function

Authors

Abstract

Related Articles