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2013 IEEE 31st International Conference on Computer Design (ICCD)

Rationale for a 3D heterogeneous multi-core processor

Year: 2013, Pages: 154-168

Authors

Eric Rotenberg, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Brandon H. Dwiel, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Elliott Forbes, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Zhenqian Zhang, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Randy Widialaksono, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Rangeen Basu Roy Chowdhury, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Nyunyi Tshibangu, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Steve Lipa, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
W. Rhett Davis, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA  
Paul D. Franzon, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, 27695, USA
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Abstract

Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.
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