Genetic Algorithm based Approach for Low Power Combinational Circuit Testing

With the advancement in automation, periodic testing of electronic circuits during their lifetime is becoming more and more important. For such a circuit, it is thus very much necessary to reduce the power requirement during the testing phase also. This paper presents a Genetic Algorithm based formulation to solve the problem of generating a test pattern set such that it has high fault coverage and low power consumption. Exhaustive experimentation done on ISCAS85 combinational benchmark suite has shown that the this tool results in upto 78% reduction in transition activity over the original test set generated by ATPGs like ATALANTA [1].