A Built-in-Self-Test Scheme for Digital to Analog Converters

Sunil Rafeeque; Vinita Vasudevan

doi:10.1109/ICVD.2004.1261065

VLSI Design, International Conference on

A Built-in-Self-Test Scheme for Digital to Analog Converters

Year: 2004, Pages: 1027

DOI Bookmark: 10.1109/ICVD.2004.1261065

Authors

Sunil Rafeeque, Indian Institute of Technology, Madras
Vinita Vasudevan, Indian Institute of Technology, Madras

Abstract

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in digital to analog converters (DACs). The BIST scheme measures each transition and estimates non-linearity errors. It makes use of a sample and subtract circuit and a VCO. The circuit is designed using 0:35?m CMOS technology from AMS. The simulation results are included in this paper. Errors estimated using the BIST scheme simulation match well with measured errors.

Like what you’re reading?

Already a member?

Get this article FREE with a new membership!

A built-in self-test scheme for 3D RAMs
2012 IEEE International Test Conference
Relating Linearity Test Results to Design Flaws of Pipelined Analog to Digital Converters
International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)
A Built-In Self-Test Scheme for Soft Error Rate Characterization
14th IEEE International On-Line Testing Symposium
A built-in self-test approach for medium to high-resolution digital-to-analog converters
Proceedings of IEEE 3rd Asian Test Symposium (ATS)
A Code Width Built-In-Self Test Circuit for 8-bit Pipelined ADC
Systems Engineering, International Conference on
A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses
23rd IEEE VLSI Test Symposium (VTS'05)
Linearity Testing Issues of Analog to Digital Converters
International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)
Built-in Self-Calibration of On-chip DAC and ADC
2008 IEEE International Test Conference
Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Static-Linearity Enhancement Techniques for Digital-to-Analog Converters Exploiting Optimal Arrangements of Unit Elements
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Built-in-Self-Test Scheme for Digital to Analog Converters

Authors

Abstract

Related Articles