A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC

Omid Mirmotahari; Yngvar Berg

doi:10.1109/ISMVL.2004.1319932

Proceedings. 34th International Symposium on Multiple-Valued Logic

A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC

Year: 2004, Pages: 135-138

DOI Bookmark: 10.1109/ISMVL.2004.1319932

Authors

Omid Mirmotahari, University of Oslo
Yngvar Berg, University of Oslo

Abstract

In this paper we present several different proposals for implementing a multiple-valued (MV) semi-floating-gate (SFG) D-latch. This paper aims to illustrate the advantages and disadvantages of each approach. Measurements from a fabricated chip at a 0.6?m CUP process is included for verifying the detailed arguments.

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A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC

Authors

Abstract

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