Quality Electronic Design, International Symposium on
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Abstract

We present an automatic register placement technique that enables the synthesis of low-power clock trees for low-power ICs. On 7 industrial designs, comparing to (1) a commercial base flow and (2) the power-aware placement technique in [2], the technique respectively reduced clock-tree power by 19.0% and 14.9%, total power by 15.3% and 5.2% and WNS under on-chip variation (
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