Abstract
With increasing power demands in modern SoCs, macros are designed to operate in multiple low power modes depending upon the voltage value of each supply. Power Aware simulations have been recently in use for simulating and verifying these low power features at the RTL level. The supplies inside PA models of IOs are modeled as ‘reg’ type and can only carry logic values 0/1. These logic values does not completely represent the supply's analog behavior. “Voltage-Aware verification” is a solution which uses ‘real’ voltage variable which keeps watch on the actual voltage values at each point in the simulation and generates the outputs based on these values. Advanced techniques in IO designs calls for the use of complex features such as core-off, IO-off and hibernate modes which can completely be represented only using actual analog voltage values. In this work we implement a voltage-aware model for a general purpose IO and validate the same using a UPF based approach in Synopsys mvtools.