System-on-Chip for Real-Time Applications, International Workshop on
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Abstract

It is well known that functional verification is a real bottleneck in any digital design development. A robust verification strategy should specify which testbenches are required to verify a system. With a modular system, the determination of which testbenches are required to confirm successful integration of each module is generally done in an ad-hoc fashion. In this paper, we propose a systematic approach supported by a tool to determine effective module combinations that should be verified when integrating a modular system. A goal of verification being to detect errors, it is valuable to create the most favorable situation to detect them. Our proposed approach is based on a static dependence analysis of a transaction-level model and the evaluation of module combinations using a verifiability metric. Using our methodology, we are able to provide quantitative results in order to help verification engineers determine which module combinations are the most appropriate for integration.
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