Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization

Three-dimensional (3D) core-based system-on-chips (SoCs) provides a promising solution to continue Moore’s law, but it also brings challenging problems, one of which is the 3D core-based SoC testing problem. Note that core tests include external tests and BIST (built-in-self-test). In addition to test time minimization, for a 3D IC, the allocation of wrapper chains (for external tests) and the allocation of BIST controllers are also important issues. In this talk, we will introduce two algorithms for 3D core-based SoC testing. First, we will present a 3D test wrapper chain synthesis algorithm (for external tests) to minimize the test time under a given TSV (through-silicon-vias) count constraint. Second, we will present a 3D BIST controller allocation algorithm to minimize the test time under a given power constraint. Benchmark data consistently show that the two proposed algorithms work well in practice.