HLDTL: High-performance, low-cost, and double node upset tolerant latch design

Aibin Yan; Zhengfeng Huang; Maoxiang Yi; Jie Cui; Huaguo Liang

doi:10.1109/VTS.2017.7928930

2017 IEEE 35th VLSI Test Symposium (VTS)

HLDTL: High-performance, low-cost, and double node upset tolerant latch design

Year: 2017, Pages: 1-6

DOI Bookmark: 10.1109/VTS.2017.7928930

Authors

Aibin Yan, School of Computer Science and Technology, Anhui University, Hefei, China
Zhengfeng Huang, School of Electronic Science & Applied Physics, Hefei University of Technology, China
Maoxiang Yi, School of Electronic Science & Applied Physics, Hefei University of Technology, China
Jie Cui, School of Computer Science and Technology, Anhui University, Hefei, China
Huaguo Liang, School of Electronic Science & Applied Physics, Hefei University of Technology, China

Abstract

This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique, and high-speed transmission path, the latch also performs with lower cost penalties. Simulation results have demonstrated the DNU tolerability and a ∼97.78% area-power-delay product saving for the latch design on average compared with the DNU tolerant latch designs.

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HLDTL: High-performance, low-cost, and double node upset tolerant latch design

Authors

Abstract

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